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Online Resumes with "unix"
Mercury Interactive (QTP, LoadRunner 8, ALM/Quality Center 9/Test Director), PVCS Tracker, Rational Clear Case, Rational Clear Quest, Load Runner) * UNIX, Windows 95/NT/2000, Sun Solaris, MS-Dos, LINUX, VMWare * J2EE, C, C++, Java, .NET (C#), VB, VC++, COBOL, JCL, CICS, XML * ODBC, JDBC, EJB, JSP, HTML, ASP, MQ Series, SOAP * Shell Scripting, VB script, Java Script * Web Logic, Apache, IBM Web Sphere 6.0, OAS and IIS * Orac...
Ideal Companies: IT project management,
Ideal Companies: USAA, Toyota, Federal Government, Allstate, AT&T, Verizon, Facebook, Texas Instruments, Baylor Health, Charles Schwab, American Airlines, Southwest Airlines, Amazon, Tesla Motors, Citi
Ideal Companies: Design Engineer
and Skillsets Possesses a BS degree in Computer Science and Mathematics. Extensive working experience in software engineering supporting U.S. Military. Experience with CMD WEB Server, Common GOTS/COTS Software, JBC-P NOC, JBC-P FSS, ABCS, BCS3, C4ISR and MC Test Support. Areas of systems testing proficiency include DB2, SQL Server, ORACLE, Linux/Unix and PARADOX. * Experience in Command, Control, Communications, Computers,...
Experience in architecture, design, development and support of Real-Time Trading Floor Distributed Systems, Core Java and J2EE Programming, Complex event processing (CEP), UNIX System and Network Programming, Database Management Client/Server Systems, UNIX System Administration, Sybase SQL Server Administration.
Tags for this Online Resume: STP, Triggers, Extensible Markup Language (XML), Java 2 Enterprise Edition (J2EE), API, Application Program Interface, Shell Script, Java Naming and Directory Interface, Lightweight Directory Access Protocol, Microsoft Windows 7
ASIC/SoC/FPGA Digital Design and Verification Engineer - 2 Years of Experience in ASIC Design and 1 Year experience in Verification Domain- Near 95825
Seeking Full-Time/Internship in ASIC/SoC Design Verification/Validation/FPGA. Two years hands on Experience in RTL design and 1 year experience in Verification, including RTL Design, Verilog HDL/ System Verilog, UVM, Code Coverage, Static Timing Analysis (STA), Functional Coverage, Assertions.
Ideal Companies: Intel, Synopsys, Xilinx, NXP, ASIC North, Segate, Mentor Graphics, Ericssion, Qlogic, Marvell, Qualcomm, Nvidia, RADIANSYS, EncoreSemi, Cirrus Logic, ARM, IBM, HCL, Amiga Infotech, L&T, CISCO, Synaptics, AMD, Broadcomm, CTG, Ambrella, Micron, Microchip, Cybercoders, OSI Semiconductors, Google, Microsoft, Facebook, Western Digital, Global Foundries, jma wIRELESS
Tags for this Online Resume: C++ Programming Language, Cadence, Coding, Compiler, Cyclic Redundancy Code (CRC), FPGA, Graphic Design, Linux, Matlab, SoC, CDC, UVM, Code Coverage, Functional Coverage, System Verilog Assertions (SVA), RTL, CMOS, System Verilog, Self checking, Constrained random teatbench, Direct Testbench, Xilinx Spartan 3E FPGA, PERL/ tcl, : Linux, Unix, Windows, Mac, DVS Protocol, MESI Protocol, UART, SPI, DDR, PCI, PCIe(Begineer), Concept of Pipeline and Hazards, Addressing Mode, Cache, Cache Mapping, Virtual Memory, Paging, DMA, ASIC, Synopsys VCS, QuestaSim, ModelSim Simulator Mentor Graphics, Cadence Virtuoso, Design Compiler, Cadence Pspice, Xilinx ISE, Simulink, EDA Playground, C++, Object Oriented Programming, LVS, DRC