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Online Resumes with "atpg"
VLSI/ASIC hardware design - Verilog/VHDL-C/C++-Schematic/Layout
Become a qualified hardware engineer in VLSI/ASIC design area. Develop the innovative technology to improve people's life
Tags for this Online Resume: ASIC, VLSI, Verilog HDL, VHDL, C/C++, Schematic, layout, ATPG
Design for Test Engineer, RTL to GDSII, CAD, Test Development, Perl
Tags for this Online Resume: DFT, Perl, RTL to GDSII, Test Development, Placement and Route, ATPG
15 year experience at Intel - Get the job done on time with highest quality
Broad experiences in technical and business-oriented tasks, field experience with tier one customers & suppliers. Heavy involvement in critical cross-company negotiations focused on business roadmap and product planning. High energy, self-driven and very detail oriented in all aspects of responsibility. Well-rounded and highly versatile with demonstrated strengths in both people and technology management. Managing the overa...
Ideal Companies: High Tech
Tags for this Online Resume: Program manager, Project manager, Business development
To become an expert in DFT.
Tags for this Online Resume: DFT, ATPG, scan, jtag, 1500, boundary scan
Senior Level ASIC and FPGA chip design verification engineer - 20+ years experience OVM/UVM
I am seeking the ASIC or FPGA Design Verification Engineer position. I can offer extensive experience in Verilog, System Verilog or VHDL verification and design, OVM/UVM verification environments, synthesis, timing, and ATPG from start of concept to their release to physical design. I have built up OVM and SystemVerilog test environments from scratch. I have bus Interface skills in design, verification, and debug: SAS and ...
Tags for this Online Resume: Design, Verification, ASIC, OVM/UVM, SystemVerilog, FPGA, SAS/SATA
Software engineer, Santa Clara
Briefly, I am currently a graduate student at Northwestern Polytechnic University, Fremont CA, towards a Master degree in Computer Engineering. I have experience in object oriented programming like C++/Java, Spring framework and I have skills in Data structures and algorithms. I also have skills in Map reduced and cloud monitoring/computing areas.
Senior ASIC DFT Engineer
Tags for this Online Resume: asic, soc, dft, atpg, c/c
Computer Hardware Engineer - 2 Years of Experience - Near 13210
and Compared testability to ATPG. Gate sizing to optimize area and overall maximum delay using C++ November 2015 * Implemented Lagrange relaxation for circuit to optimize overall area subjected to delay less than maximum delay. * Developed C++ source code using classes to implement both algorithm and successfully achieve excellent result.* Designed 8 --bit Microprocessor ASIC with AMI 0.6um
Tags for this Online Resume: Altera, C Programming Language, C/C++ Programming Languages, Cadence, Electronic Design Automation (EDA), Electronics, Engineering, Matlab