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Online Resumes with "SystemVerilog"
Performed ASIC chip design and verification at component level as well as chip level using various HDLs like SystemVerilog and Verilog. Provided automation using Perl, Shell, Make scripting languages. Performed Coverage Driven Verification (CDV) and wrote
Looking forward to work as an ASIC design/verification engineer. In my professional experience of 2.5+ years, I've extensively worked on SystemVerilog and Verilog to perform verification of various standard protocols like SDIO, MMC, USB2.0, PCI, AHB AMBA, UART, I2C, Wishbone. Have developed Perl, Shell, Make scripts to provide automation. Also worked on various verification methodologies like OVM, VMM, AVM. I'd be glad to s...
Experienced in functional verification of large VLSI designs
Ideal Companies: Broadcom Intel EMC NetworkAppliance
To land a verification position using SystemVerilog.
To work in a challenging environment, where I can effectively utilize my skills, knowledge, experience and potential towards the growth of the organization.
Professional Experience: Working as Member of Technical Staff at PW systems/Ichip Technologies, Hyderabad from Oct 2008 to till date. Worked as Verification Engineer at StellarIP Solutions, Hyderabad from Feb 2007 to Sep 2008. Got Cadence EDA tools Experience for Full Custom ASIC Design while doing Advanced PG Diploma in VLSI design in VEDANT, Chandigarh certified by Semiconductor Complex Ltd under Cadence Universi...
Tags for this Online Resume: VLSI design Tools Simulation: ModelSim, Synopsys VCS, Cadence NC-Sim Implementation: Xilinx ISE 9.1i Tools: Specman, NC-Verilog, Vbuilder, Leonardo- Spectrum, ICFB (Spectre, Virtuoso, Assura), SOC Encounter, Co-ware Processor. Skills
I am seeking the ASIC or FPGA Design Verification Engineer position. I can offer extensive experience in Verilog, System Verilog or VHDL verification and design, OVM/UVM verification environments, synthesis, timing, and ATPG from start of concept to their release to physical design. I have built up OVM and SystemVerilog test environments from scratch. I have bus Interface skills in design, verification, and debug: SAS and ...
Rami Attas Tel: 972-52-5597916 Email: firstname.lastname@example.org Education: Technion Institute Electrical Engineering Faculty; (B.Sc.) Professional experience: Designing electronic systems composed from microprocessors and digital logic, hardware and software integration. Implementation designs in FPGA. Building verification environment in HDL using modelsim tool. Recently I researched Zynq component Programming: VHDL, VERILOG, ...
Graduate student in Electrical Engineering at UCCS seeking a technically oriented position where I can apply my coursework and skills. I am very familiar with Verilog RTL coding and Design Verification using SystemVerilog. I am highly motivated, a team player and have good interpersonal and communication skills.
SUMMARY •US permanent resident fully authorized to work in the US (Green Card, EB-11) •PhD in Electronic Engineering from The University of Tokyo in Japan and Xi’an Jiaotong University •10 years hardware and chips experience including the development of video and image processing/monitoring chips, Closed loop trajectory correction system chips based on real time graph and image feedback, Video codec development based on H....
Actively seeking an opportunity in the field of VLSI where I can put my engineering skills into practice & develop myself along with the development of the organization. ACADEMICS: * MS in Electrical Engineering GPA: 3.350 San Jose State University, San Jose, CA August 2015 - May 2017 Related Coursework: Logic Design for DSP/Communication, Advanced Logic Design, Probability- Random Variables and Stochastic Process, Advanced...