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Online Resumes with "SOC Encounter"
Physical design Engineer
I have six years of experience in Physical Design. I am currently working on the technology scale down project at ARM as contractor. I have exposure to the prominent tools from Synopsys, Mentor Graphics and Cadence like IC Compiler, Astro, AstroRail, StarRC-XT, PrimeTime,PrimeRail, Calibre, SOC Encounter and Nano Router.
Tags for this Online Resume: physical design , ASIC designer, Cadence, IC Compiler, Caliber, Synopsys
5 years of experience in Physical Design. I have exposure to the prominent tools from Synopsys, Mentor Graphics and Cadence like IC Compiler, Astro, AstroRail, StarRC-XT, PrimeTime,PrimeRail, Calibre, SOC Encounter and Nano Router.
Seeking a challenging and enduring job in professional organization where my skills & abilities could be fully utilized to achieve organizational goals and professional growth.
Tags for this Online Resume: Physical design engineer, IC Compiler, SOC Encounter, Calibre, Primtime, PTSI
RESUME
Satish Chakkirala 1746 Ximeno Avenue, Apt # 5 Long Beach, CA - 90815 (714)-7944564 satish.0722@gmail.com OBJECTIVE An internship/full time position in the field of Electronics Engineering. Quest to work in a real professional environment, where I can enhance my skills and widen spectrum of knowledge. Also to make an indelible mark in the organization that i serve. Education •California State University Long beach...
To work in a challenging environment, where I can effectively utilize my skills, knowledge, experience and potential towards the growth of the organization.
Professional Experience: Working as Member of Technical Staff at PW systems/Ichip Technologies, Hyderabad from Oct 2008 to till date. Worked as Verification Engineer at StellarIP Solutions, Hyderabad from Feb 2007 to Sep 2008. Got Cadence EDA tools Experience for Full Custom ASIC Design while doing Advanced PG Diploma in VLSI design in VEDANT, Chandigarh certified by Semiconductor Complex Ltd under Cadence Universi...
Ideal Companies: synopsys, cadence, AMD, Cisco, Wipro
Tags for this Online Resume: VLSI design Tools Simulation: ModelSim, Synopsys VCS, Cadence NC-Sim Implementation: Xilinx ISE 9.1i Tools: Specman, NC-Verilog, Vbuilder, Leonardo- Spectrum, ICFB (Spectre, Virtuoso, Assura), SOC Encounter, Co-ware Processor. Skills
Electronics Engineer - 12 Years of Experience - Near 94041
Profile: Experience in * Fullchip backend design integration, management, * Chip level edit, floor plaining and tapeout. * Analog and digital customer layout. * I/O PAD, memory full custom layout design including floor planning. * Has the certificate of the Cadence First and SOC Encounter * Using Laker tool generate the sub block automatically, and it's DRC and LVS. * Physical design, LVS, DRC and RC extraction and verifica...
Tags for this Online Resume: Layout, Management, Planning, Tape-out, Asic, Chip Design, Multimedia, CAD Tools, Cadence, Chip Verification
Electronics Engineer - 16 Years of Experience - Near 94041
Profile: Experience in * Fullchip backend design integration, management, * Chip level edit, floor plaining and tapeout. * Analog and digital customer layout. * I/O PAD, memory full custom layout design including floor planning. * Has the certificate of the Cadence First and SOC Encounter * Using Laker tool generate the sub block automatically, and it's DRC and LVS. * Physical design, LVS, DRC and RC extraction and verifica...
Tags for this Online Resume: Layout, Management, Planning, Asic, Chip Design, Multimedia, Tape-out, CAD Tools, Cadence, Chip Verification
