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Online Resumes with "RTL Design"



FPGA Engineer

Actively Looking for Co-op/ Full time position in the field of Design Verification, RTL Design, Physical Design, Computer Architecture, FPGA/ASIC Design.

System Engineer - 2 Years of Experience - Near 90007

Hello! I am an Electrical Engineering Graduate student at USC actively seeking Full Time Position/Co-Op Internship opportunities in roles requiring Digital ASIC RTL Design/DV, Computer Architecture, VLSI Physical Design, FPGA prototyping and DFT testing. I have been very passionate about Computer Architecture and Digital RTL design for the longest time I can remember, and hence I will go beyond the call of duty for job req...

Tags for this Online Resume: asic, cpu, design, verification, entry-level new graduate, fpga , dft

Computer Hardware Engineer - 20 Years of Experience - Near 95070

SUMMARY * Achieved "First Silicon" success on multiple products * Extensive experience in RTL design of ASIC/SOC products * Managed Multi-geography Development Teams of over 30 Engineers * Managed Both RTL Design and Verification Teams * Led Cross-Functional Project/Product Teams * Developed Metrics and Methodologies for Engineering Teams * RTL Developer of 14 ASICs as Individual Contributor

Tags for this Online Resume: Asic, Hardware, Logic Design, Management, RTL, Project Management, San Jose, SOC, Scheduling, Manufacturing

Electrical Engineer - Graduated 2017 - Near 95051

Actively seeking an opportunity in the field of VLSI where I can put my engineering skills into practice & develop myself along with the development of the organization. ACADEMICS: * MS in Electrical Engineering GPA: 3.350 San Jose State University, San Jose, CA August 2015 - May 2017 Related Coursework: Logic Design for DSP/Communication, Advanced Logic Design, Probability- Random Variables and Stochastic Process, Advanced...

Tags for this Online Resume: Automation, Documentation, Failure Analysis, Troubleshooting, VLSI, SoC Design, UVM, Cadence, RTL design/ Verification, ASIC, Verilog, SystemVerilog, VHDL, Python