CV, Curriculum Vitae and Online Resumes Search
Recruiters - Try Postings!
Postings.com™ is a must-have for recruiters who want to:
- Find Qualified Candidates
- Find Job orders and Post Splits
- Be Found in Search Engines
- Implement a Social Sourcing Strategy
Job Seekers - Look Here!
Hitting a wall with your job search? Try Climber Premium.
- Top the Search Engines
- Unsurpassed Candidate Marketing
- Power Career Networking
- Fresh Jobs from the Net
Were you looking for ATPG job results?
Click Here to search for ATPG in our 2.4M jobs.
Online Resumes with "ATPG"
Become a qualified hardware engineer in VLSI/ASIC design area. Develop the innovative technology to improve people's life
Design for Test Engineer, RTL to GDSII, CAD, Test Development, Perl
Broad experiences in technical and business-oriented tasks, field experience with tier one customers & suppliers. Heavy involvement in critical cross-company negotiations focused on business roadmap and product planning. High energy, self-driven and very detail oriented in all aspects of responsibility. Well-rounded and highly versatile with demonstrated strengths in both people and technology management. Managing the overa...
Ideal Companies: High Tech
To become an expert in DFT.
I am seeking the ASIC or FPGA Design Verification Engineer position. I can offer extensive experience in Verilog, System Verilog or VHDL verification and design, OVM/UVM verification environments, synthesis, timing, and ATPG from start of concept to their release to physical design. I have built up OVM and SystemVerilog test environments from scratch. I have bus Interface skills in design, verification, and debug: SAS and ...
Briefly, I am currently a graduate student at Northwestern Polytechnic University, Fremont CA, towards a Master degree in Computer Engineering. I have experience in object oriented programming like C++/Java, Spring framework and I have skills in Data structures and algorithms. I also have skills in Map reduced and cloud monitoring/computing areas.
and Compared testability to ATPG. Gate sizing to optimize area and overall maximum delay using C++ November 2015 * Implemented Lagrange relaxation for circuit to optimize overall area subjected to delay less than maximum delay. * Developed C++ source code using classes to implement both algorithm and successfully achieve excellent result.* Designed 8 --bit Microprocessor ASIC with AMI 0.6um