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RssSenior Level ASIC and FPGA chip design verification engineer - 20+ years experience OVM/UVM

I am seeking the ASIC or FPGA Design Verification Engineer position. I can offer extensive experience in Verilog, System Verilog or VHDL verification and design, OVM/UVM verification environments, synthesis, timing, and ATPG from start of concept to their release to physical design. I have built up OVM and SystemVerilog test environments from scratch. I have bus Interface skills in design, verification, and debug: SAS and SATA interface design and debug; 1394B bus interface verification; PCI and PCI-X Bus design and debug; 1553 bus interface. I can work well independently, or as a team member. I have skills in leading small teams as well.

Electrical Engineer

About Me


Engineering & Architecture


Electrical Engineer

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