Climber_bannerad_300x250_15s

Want your profile here?

Becoming a member is easy!

Climber.com works with you to help you advance your career by putting you directly in front of tens of thousands of recruiters in your field. Just fill out the form below to start your account.

Sign up today!



Jobs_start_here

Recruiters - Try Postings!

Postings.com™ is a must-have for recruiters who want to:

  • Find Qualified Candidates
  • Find Job orders and Post Splits
  • Be Found in Search Engines
  • Implement a Social Sourcing Strategy

RssRESUME

Satish Chakkirala 1746 Ximeno Avenue, Apt # 5 Long Beach, CA - 90815 (714)-7944564 satish.0722@gmail.com OBJECTIVE An internship/full time position in the field of Electronics Engineering. Quest to work in a real professional environment, where I can enhance my skills and widen spectrum of knowledge. Also to make an indelible mark in the organization that i serve. Education •California State University Long beach : Pursuing Masters in Electrical Engineering Major : Electronics /GPA 3.3, Expected graduation date May 2009. •Jawaharlal Nehru Technological University : Bachelors Degree in Electronics & communications Engineering /GPA 3.0. Relevant Course Work CMOS Electronics, VLSI Design, Mixed Signal IC Design, Analog electronic circuits, Design of Digital Filters and Audio processing, Circuit Synthesis, Advanced Circuit Synthesis, Linear Systems Analysis, Robot Dynamics and control. Professional Development Experience •Worked as an intern, VLSI Design at “COREL TECHNOLOGIES” an authorized training center in association with XILINX at BANGLORE in INDIA. •Professional development Course in an authorized training center of XILINX.. •Worked as an intern in INDIA at “CMC Limited A TATA Enterprise”, as a part of academic curriculum from January 07 to April 07. The training was emphasized on the project “GSM Based Hazard Detection System” using the tools Embedded Systems, MSP (IAR Work Bench). ACADEMIC Projects VLSI Front end(Logic Design) projects •Demonstrated Colour spectrum , Moving geometrical object on 640*480 VGA display using SPARTAN3 starter kit & debugging/monitoring using Chip scope Pro. •Designed the RTL module for an FSL core with data loop back. Verifyed the design by writing an image data to the input side of FSL bus and read the image data from the output side of FSL bus. •Designed UART(Universal Asynchronous Receiver and Transmitter) for transmitting data from one computer(Receiver) to another computer(Transmitter) simultaneously. Debugged/monitored using Chip scope Pro. •Demonstrated a sample application using Xilinx TFT controller with MicroBlaze processor system , read BMP images from CFC and streamed them to VGA display. •Designed DISCRETE COSINE TRANSFORM AND QUANTIZATION PROCESSOR AND CONTROLLER for video or image compression using a novel parallel algorithm for fast implementation and verifyed the results with the results obtained from MATLAB tool.. •Designed PHERIPHERAL COMPONENT INTERFACE which is a video application using ASM chart. •Designed SINGLE ADDRESS & DUAL ADDRESS ROM ON F.P.G.A or ASIC . •Designed DUAL RAM on F.P.G.A or ASIC. •Designed CONTROLLER to interface EXTERNAL RAM with F.P.G.A OR ASIC. •Designed Arithmetic circuits such as SERIAL & PARALLEL PIPELINED ADDER , SERIAL &PARALLEL PIPELINED SUBTRACTOR, PARALLEL PIPELINED MULTIPLIER using an algorithm for fast implementation. •Designed a CALUCLATOR.. •Designed 7- Segment Marquee cum Counter, Boundary scan test, Barrel Shifter using VERILOG and VHDL. VLSI Front end(Logic Design )Skills • Possess strong knowledge of digital basics. • Possess good understanding and knowledge on FPGA architecture, FPGA as a system component, Programmable logic, FPGA configurations, logic mapping to the F.P.G.A, FPGA-Memory, Processor, DSP/multipliers, Gigabit I/Os, Clock management components ,FPGA Editor. • Possess good understanding and knowledge on LOGIC DESIGN using VERILOG & VHDL languages, RTL coding , Design Flow, Design implementation, Design abstractions, Design hierarchy, Writing Test benches, Simulation ,Synthesis ,Static timing analysis, Timing constraints, Area constraints, FPGA pin assignments, Usage of Xilinx core gen and libraries, Debugging/monitoring using Chip scope Pro, Designing with the Plan ahead analysis and design tool, Development stages, Configuration management version control ,Verification planning, Usage of Scripts for simulation. •Good understanding of design for verification methodologies. •Embedded system design on FPGA , configuration of Hardware and Software platform for Embedded System Design. •Design and Verification of DSP application on FPGA. •Multi Gigabit Transceivers, Serial IO, line encoding, Clock correction, Applications of MGT. VLSI Back end(physical Design) projects •Designed transistor level schematics and physical layouts for Inverter, OP-Amp, A/D converter, D/A convertor, uA71 op-amp , Current Bias circuit, differential amplifier, Comparator,& performed Design Rule Check (DRC) on the layouts, performed LVS, extracted the layouts and performed simulations using Spectre and then combining all these macro blocks Layouts as well as standard cells to design Analog chip . •Designed transistor level schematics and physical layouts for Digital- TO- Analog Convertor(90nm) using Successive approximation. Performed Design Rule Check (DRC) on the layouts, performed LVS, extracted the layouts and performed simulations using spectre. •Designed transistor level schematics and physical VLSI layouts for FLASH ANALOG- TO- DIGITAL CONVERTER(90nm) , & performed Design Rule Check (DRC) on the layouts, performed LVS, extracted the layouts and performed simulations using Spectre. TECHNICAL SKILLS •Electrical Tools: Cadence, XILINX-ISE , MODELSIM 6.4a, System generator, PSPICE •Cadence Virtuoso Layout Editor, Composer Schematic Editor, Diva DRC/ LVS/ Extract, Analog Design Environment, Spectre, SOC Encounter-XL( Placement and Routing) ,Incisive Unified Simulator (Simulation)cadence software, RTL Compiler XL (Compiler), Virtuoso XL Layout Editor(Layout), Assura DRC/LVS. (Physical Verification), Assura RC (RC extraction), Virtuoso Schematic Entry, Celtic Cross Talk Analysis for Signal Integrity Analysis, Voltage Storm IR drop analysis Tools for Signal Integrity Analysis, Nano Route Global/Detail Router (Nano Routing), Analysis using Verilog-A, Verilog-XL, Verilog-AMS. •Programming skills: Verilog, C, C++,VHDL, Verilog-A, Verilog-XL, System Verilog,System generator.. •Operating Systems: Linux, Dos, Windows 9x/NT/XP/Vista, Ms office2000/XP word, power point. •Experience with various oscilloscopes, logic analyzers, Multimeters , Function Generators. Satish Chakkirala 1746 Ximeno Avenue, Apt # 5 Long Beach, CA - 90815 (714)-7944564 satish.0722@gmail.com OBJECTIVE An internship/full time position in the field of Electronics Engineering. Quest to work in a real professional environment, where I can enhance my skills and widen spectrum of knowledge. Also to make an indelible mark in the organization that i serve. Education •California State University Long beach : Pursuing Masters in Electrical Engineering Major : Electronics /GPA 3.3, Expected graduation date May 2009. •Jawaharlal Nehru Technological University : Bachelors Degree in Electronics & communications Engineering /GPA 3.0. Relevant Course Work CMOS Electronics, VLSI Design, Mixed Signal IC Design, Analog electronic circuits, Design of Digital Filters and Audio processing, Circuit Synthesis, Advanced Circuit Synthesis, Linear Systems Analysis, Robot Dynamics and control. Professional Development Experience •Worked as an intern, VLSI Design at “COREL TECHNOLOGIES” an authorized training center in association with XILINX at BANGLORE in INDIA. •Professional development Course in an authorized training center of XILINX.. •Worked as an intern in INDIA at “CMC Limited A TATA Enterprise”, as a part of academic curriculum from January 07 to April 07. The training was emphasized on the project “GSM Based Hazard Detection System” using the tools Embedded Systems, MSP (IAR Work Bench). ACADEMIC Projects VLSI Front end(Logic Design) projects •Demonstrated Colour spectrum , Moving geometrical object on 640*480 VGA display using SPARTAN3 starter kit & debugging/monitoring using Chip scope Pro. •Designed the RTL module for an FSL core with data loop back. Verifyed the design by writing an image data to the input side of FSL bus and read the image data from the output side of FSL bus. •Designed UART(Universal Asynchronous Receiver and Transmitter) for transmitting data from one computer(Receiver) to another computer(Transmitter) simultaneously. Debugged/monitored using Chip scope Pro. •Demonstrated a sample application using Xilinx TFT controller with MicroBlaze processor system , read BMP images from CFC and streamed them to VGA display. •Designed DISCRETE COSINE TRANSFORM AND QUANTIZATION PROCESSOR AND CONTROLLER for video or image compression using a novel parallel algorithm for fast implementation and verifyed the results with the results obtained from MATLAB tool.. •Designed PHERIPHERAL COMPONENT INTERFACE which is a video application using ASM chart. •Designed SINGLE ADDRESS & DUAL ADDRESS ROM ON F.P.G.A or ASIC . •Designed DUAL RAM on F.P.G.A or ASIC. •Designed CONTROLLER to interface EXTERNAL RAM with F.P.G.A OR ASIC. •Designed Arithmetic circuits such as SERIAL & PARALLEL PIPELINED ADDER , SERIAL &PARALLEL PIPELINED SUBTRACTOR, PARALLEL PIPELINED MULTIPLIER using an algorithm for fast implementation. •Designed a CALUCLATOR.. •Designed 7- Segment Marquee cum Counter, Boundary scan test, Barrel Shifter using VERILOG and VHDL. VLSI Front end(Logic Design )Skills • Possess strong knowledge of digital basics. • Possess good understanding and knowledge on FPGA architecture, FPGA as a system component, Programmable logic, FPGA configurations, logic mapping to the F.P.G.A, FPGA-Memory, Processor, DSP/multipliers, Gigabit I/Os, Clock management components ,FPGA Editor. • Possess good understanding and knowledge on LOGIC DESIGN using VERILOG & VHDL languages, RTL coding , Design Flow, Design implementation, Design abstractions, Design hierarchy, Writing Test benches, Simulation ,Synthesis ,Static timing analysis, Timing constraints, Area constraints, FPGA pin assignments, Usage of Xilinx core gen and libraries, Debugging/monitoring using Chip scope Pro, Designing with the Plan ahead analysis and design tool, Development stages, Configuration management version control ,Verification planning, Usage of Scripts for simulation. •Good understanding of design for verification methodologies. •Embedded system design on FPGA , configuration of Hardware and Software platform for Embedded System Design. •Design and Verification of DSP application on FPGA. •Multi Gigabit Transceivers, Serial IO, line encoding, Clock correction, Applications of MGT. VLSI Back end(physical Design) projects •Designed transistor level schematics and physical layouts for Inverter, OP-Amp, A/D converter, D/A convertor, uA71 op-amp , Current Bias circuit, differential amplifier, Comparator,& performed Design Rule Check (DRC) on the layouts, performed LVS, extracted the layouts and performed simulations using Spectre and then combining all these macro blocks Layouts as well as standard cells to design Analog chip . •Designed transistor level schematics and physical layouts for Digital- TO- Analog Convertor(90nm) using Successive approximation. Performed Design Rule Check (DRC) on the layouts, performed LVS, extracted the layouts and performed simulations using spectre. •Designed transistor level schematics and physical VLSI layouts for FLASH ANALOG- TO- DIGITAL CONVERTER(90nm) , & performed Design Rule Check (DRC) on the layouts, performed LVS, extracted the layouts and performed simulations using Spectre. TECHNICAL SKILLS •Electrical Tools: Cadence, XILINX-ISE , MODELSIM 6.4a, System generator, PSPICE •Cadence Virtuoso Layout Editor, Composer Schematic Editor, Diva DRC/ LVS/ Extract, Analog Design Environment, Spectre, SOC Encounter-XL( Placement and Routing) ,Incisive Unified Simulator (Simulation)cadence software, RTL Compiler XL (Compiler), Virtuoso XL Layout Editor(Layout), Assura DRC/LVS. (Physical Verification), Assura RC (RC extraction), Virtuoso Schematic Entry, Celtic Cross Talk Analysis for Signal Integrity Analysis, Voltage Storm IR drop analysis Tools for Signal Integrity Analysis, Nano Route Global/Detail Router (Nano Routing), Analysis using Verilog-A, Verilog-XL, Verilog-AMS. •Programming skills: Verilog, C, C++,VHDL, Verilog-A, Verilog-XL, System Verilog,System generator.. •Operating Systems: Linux, Dos, Windows 9x/NT/XP/Vista, Ms office2000/XP word, power point. •Experience with various oscilloscopes, logic analyzers, Multimeters , Function Generators.

Electronics Engineer

Long Beach, CA

About Me

Industry:

Engineering & Architecture

Occupation:

Electronics Engineer
 

Education level:

Master

Will Relocate:

Yes

Location:

Long Beach, CA