Chan-Yun L

Engineering Manager - 15 Years of Experience - Near 94536


Engineering Manager


Fremont, CA

Education Level:


Will Relocate:



SUMMARY: Results oriented professional with extensive education/industry background, skills, and proven expertise including: * Ph.D. in Physics * More than 15 years in semiconductor industry research, development, manufacturing management, engineering, and international accounts * Conducted and analyzed research on IC processing techniques * Designed and supervised the manufacturing process of silicon wafers * Performed silicon crystal and amorphous thin films growth * Proven ability to solve software and hardware problems * Solid leadership skills * Led scientific group in setting up two new physics laboratories and updated experimental equipment * Several years of teaching semiconductor physics courses and laboratories * Authored publications in the field of semiconductor physics * Achieved several recognition awards Key Accomplishments: Plasma Etch and Thin Film Technology * Research and development of new highly integrated electronics & photonics circuits. Pioneering R&D Inventions in new processes and materials. * Led projects to develop 110, 90, 65, 45, 32nm technology nodes on both logic and memory products. * Managed key accounts and helped develop 32nm etch technology which has been maturely developed and delivered to product lines. Currently 22nm dielectric etch process is ready and being transferred to mass production for major IC chip manufacturers. The 12/10nm technology with double patterning technique (DPT) is recent focus point. * Initiated research projects to develop and implement new clean room chip fabrication technologies. * Assisted the worldwide major IC manufacturers in solving yield-related issues, including high particle counts, polymer peeling, bridging, block etch, plasma damage, endpoint malfunction, etc. * Initiated and implemented several research projects to develop the most challenging via veil removal and high selectivity low-k processes on a new chemical downstream etch tool. Results have been patented. * Directed research projects to develop low-k dual damascenes processes in different feature sizes and film stacks. Results were presented in ICMI 2000 and IITC 2001. * Developed the most advanced oxide etches: multi-level Contact, Via, HAR, SAC, bi-layer and tri-layer dry etch process for worldwide major IC chip manufacturers. The first world SAC process on high-density plasma TCP etcher for 0.7um x 0.38um feature size has been successfully developed with satisfactory production yields. Results were presented to 1997 Semicon Taiwan. * Took advantage of the plasma sputtering machines and ultrahigh vacuum techniques to grow different types of semiconductor thin films. Studied and applied their physical properties in semiconductor devices design. Performed failure analysis using SEM, and CD SEM. * Applied FLIR IR technology to study plasma/chamber temperature distribution, heat flux variation, and parts reliability, etc. * Developed new reducing chemistry process and its capability of cleanliness has been verified. Very high selectivity of resist to amorphous carbon has been achieved and patents filed.